1. Field of the Invention
The present invention relates to non-volatile memory devices.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Typical EEPROMs and flash memories utilize a memory cell with a floating gate that is provided above a channel region in a semiconductor substrate. The floating gate is separated from the channel region by a dielectric region. For example, the channel region is positioned in a p-well between source and drain regions. A control gate is separated from the floating gate by another dielectric region (inter-gate or inter poly dielectric). The threshold voltage of the memory cell is controlled by the amount of charge that is retained on the floating gate. That is, the level of charge on the floating gate determines the minimum amount of voltage that must be applied to the control gate before the memory cell is turned on to permit conduction between its source and drain.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states (e.g. a binary memory cell). A multi-bit or multi-state flash memory cell is implemented by identifying multiple, distinct threshold voltage ranges within a device. Each distinct threshold voltage range corresponds to predetermined values for the set of data bits. To achieve proper data storage for a multi-state cell, the multiple ranges of threshold voltage levels should be separated from each other by sufficient margin so that the level of the memory cell can be read, programmed or erased in an unambiguous manner.
When programming typical flash memory devices, a program voltage is applied to the control gate and the bit line is grounded. Due to capacitive coupling between the control gate and floating gate, the program voltage on the control gate is coupled to the floating gate causing a floating gate voltage. The floating gate voltage causes electrons from the channel to be injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell as seen from the control gate is raised. In order to preserve the programmed state of the memory cell, the charge on the floating gate needs to be maintained over time. However, it is possible for charge to leak through the inter-poly dielectric from the floating gate to the control gate, which is referred to as leakage current.
In recent flash memory technologies, short program/erase times and low operating voltages are the main obstacles to overcome in order to realize high speed and density, and low power operation. Thus, it has become increasingly necessary to increase the capacitive coupling between the floating gate and the control gate of the memory cell, while simultaneously inhibiting electrons from escaping from the floating gate to the control gate. The control gate-to-floating gate capacitance, which affects the coupling ratio, depends upon the thickness of the inter-poly dielectric (IPD) between the two gates and the relative permittivity or dielectric constant, K, of the IPD. One technique to achieve a high coupling ratio is to use a thin IPD. However, if the IPD is too thin, the leakage current can become undesirably large.
As non-volatile memory structures become smaller, leakage current is becoming a more difficult problem. One reason for the leakage current problem is the strength of the electric field that occurs in various portions of the IPD when a voltage is applied to the control gate. In particular, the electric field is enhanced in certain regions of the IPD, which results in greater leakage current. Referring to FIG. 1A, the electric field is the strongest in the IPD 106 near sharp corners of the floating gate 102 and control gate 104. In the region near the corner of the IPD 106 that is circled, the magnitude of the electric field is proportional to 1/A, where A is the radius of curvature of the corner of the floating gate 102. Note that a sharp corner corresponds to a very small radius of curvature, and hence a strong electric field.
In order to reduce the strength of the electric field in the IPD 106 at the corner of the floating gate 102, the radius of curvature of the top of the floating gate 102 can be increased, as depicted in FIG. 1B. Note this also changes the curvature of the control gate 104. By reducing the strength of the electric field, the leakage current is reduced. However, in order to continue to scale down the size of device structures, it is desirable to narrow the width of the floating gate 102, as depicted in FIG. 1C. Note that the rounding of the polysilicon floating gate 102 extends completely across the top of the floating gate 102 of FIG. 1C. The amount of rounding of the floating gate 102 that is possible is limited by the width of the floating gate 102. That is, the largest possible radius of curvature (A) is limited to half the width of the floating gate 102. Note that if the width (2A) of the floating gate 102 is further reduced, the maximum possible radius of curvature is also further reduced. Therefore, as feature sizes of memory cells continue to be reduced, the electric field in the IPD 106 and hence leakage current becomes more difficult to deal with.
One technique to reduce the electric field is to form the IPD 106 with a thin film having a high dielectric constant. However, such films are difficult to work with and hence undesirable. For example, paraelectric materials have dielectric constants that are usually at least two orders of magnitude above that of silicon dioxide, but several problems limit their use as gate dielectrics. One such problem is oxygen diffusion. During high temperature processes associated with semiconductor fabrication, oxygen diffuses from the IPD 106 to the interface between the IPD 106 and the floating gate 102 and control gate 104 that sandwich the IPD 106, thus forming an undesirable oxide layer that decreases the overall capacitance of the dielectric system. Therefore, the effect of the high dielectric constant paraelectric material is reduced.
Metal oxides have also been proposed as high K materials for flash memory devices. Metal oxides, in particular aluminum oxide (Al2O3), have a low leakage current. Moreover, metal oxides have high temperature endurance for process integration. However, because the deposited high dielectric metal oxides have non-stoichiometric composition, they are prone to large electrical defects or traps in the bulk of the dielectric and at the dielectric/semiconductor interface. These defects or traps enhance conduction through the dielectric and reduce the breakdown strength of the dielectric.
Another technique to reduce the electric field in the IPD is to increase the thickness of the IPD 106. However, increasing the thickness of the IPD 106 tends to reduce the capacitive coupling between the floating gate 102 and the control gate 106, which is undesirable for reasons previously discussed. In general, increasing the IPD 106 thickness tends to fail when the radius of curvature is less than the thickness of the IPD 106 or when the thickness of the IPD 106 approaches the dimension (“feature size”) of the memory cell.